The Real-time VLBI Correlator (RVC) is a new type processor for the Very-Long-Baseline Interferometry (VLBI). This correlator was primarily designed for supporting the VLBI Space Observatory Programme (VSOP). Two particular techniques, the fringe rotator after correlation and the lag-time extension technique, are newly developed for the RVC. The correlation circuit size of VLBI correlator is reduced to half by introducing the new fringe rotator, and it makes possible to realize a large delay window being essential in finding a cross correlation in real-time. The delay window can be changed flexibly with the lag-time extension technique, and its technique is useful to detect the fringe peak in a VSOP observation. The new correlator was installed at the Usuda Deep Space Center in Japan, and is used in VSOP and other domestic VLBI observations. In this paper, the key features of the Real-time VLBI Correlator (RVC) focusing on these advanced techniques are presented, and the results of its performance test are shown.

A new reference voltage generator for megabit DRAMs is proposed. The supply voltage dependence of the generator is successfully suppressed in comparison with the conventional reference voltage circuit. It is shown that the Vcc Margin of DRAM operation can be noticeably improved by using this generator.

Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

We explore the maximum total number of edge crossings and the maximum geometric thickness of the Euclidean minimum-weight (k, ℓ)-tight graph on a planar point set P. In this paper, we show that (10/7－ε)|P| and (11/6－ε)|P| are lower bounds for the maximum total number of edge crossings for any ε ＞ 0 in cases (k,ℓ)=(2,3) and (2,2), respectively. We also show that the lower bound for the maximum geometric thickness is 3 for both cases. In the proofs, we apply the method of arranging isomorphic units regularly. While the method is developed for the proof in case (k,ℓ)=(2,3), it also works for different ℓ.

In situ grown Y-Ba-Cu-O films were prepared on MgO substrate by rf magnetron sputtering with dc-biased substrate holder using a stoichiometric YBa2Cu3Oz target. The films were deposited at substrate temperature Ts about 660 and various substrate holder bias voltages VH. Influence of a dc bias voltage of substrate holder on the superconducting characteristics of Y-Ba-Cu-O thin films are investigated. Films with critical temperature higher than 80 K can be obtained at bias voltages from 20 V to 80 V for 500 mTorr. The optimum bias voltage to obtain the high Tc films depends on the sputtering gas pressure. The optimum bias voltages in 500 mTorr and 300 mTorr are 20 V and 150 V, respectively. The film morphology depends on the bias voltage rather than the sputtering gas pressure in this experiment and the smooth film surface is obtained at low voltages from 20 V to 40 V. For the films deposited at 80 V in 500 mTorr, the film of 200 nm thick is smoother than films of 400 nm and 700 nm thick. The deviation of the film composition is varied by the negative holder bias voltage. The critical temperature depends on the c-lattice parameter rather than the film composition. The films with short c-lattice parameter have the high Tc. The negative holder bias is effective for obtaining the high Tc films in the low pressure. However, in the high pressure, the films at the high bias voltages have slightly low Tc as compared with films at low bias voltage.

We proposed a method for embedding binary data into JPEG bitstreams and extracting embedded data from JPEG bitstreams using the standard JPEG decoder. In the proposed method, we can decode the image from JPEG bitstreams into which the binary data is embedded first using the traditional standard JPEG decoder, and then we can extract the embedded binary data perfectly by the post-processing from the decoded JPEG image. For the post-processing, we use only the decoded image data to extract the embedded binary data. Namely, we do not need any kind of particular parameters, which are used for JPEG decoding, such as quantization table value. Thus, we can use the traditional standard JPEG decoder for the pre-processing of extracting binary data. Furthermore, we address the effect of the calculation bit accuracy of discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) for extracting embedded binary data perfectly as post-processing. Simulations using extracting embedded binary data as post-processing are presented to quantify some performance factors concerned. And we confirmed that the proposed method could be of practical use.

A sputtering system using dc hollow cathode discharge was developed for the propose of high Tc superconducting devices. Using this system, as-grown superconducting thin films of YBCO have been formed on MgO and SrTiO3 substrates. Influence of the sputtering conditions such as the substrate temperature and discharge gas pressure on the Tc and lattice parameter was investigated. It was found that superconducting films on MgO with Tczero higher than 87 K ere routinely obtained at the pressure of 820 mTorr (5%O2) and substrate temperature of 700 during deposition. The a/b-axis and c-axis oriented YBCO-PBCO hetero-structures were also successfully formed on MgO and SrTiO3 substrates.

Although larger scale integration enhances the practicability of superconducting Josephson circuits, several technical problems begin to emerge during its progress. One of the problems is the increase of current through a ground plane (ground current). Excess ground current produces additional magnetic field and reduces operation margins of the circuits, because superconducting Josephson devices are very sensitive to magnetic field. In this paper, we evaluate current distribution in a superconducting ground plane by means of both experiments and numerical calculation. We also verify two methods for suppressing the ground current. One is a slot structure in the ground plane, and the other is alignment of the current-extraction point. Suppression of the ground current is quantitatively evaluated.

The VSOP terminal is a new data-acquisition system for the Very-Long-Baseline Interferometry (VLBI). This terminal was primarily designed for ground telescopes in the VLBI Space Observatory Programme (VSOP). New technologies; higher-order sampling and digital filtering techniques, were introduced in the development. A cassette cart was also introduced, which supports 24-hour unattended operations at the maximum data rate of 256 Mbps. The higher-order sampling and digital filtering techniques achieve flat and constant phase response over bandwidth of 32 MHz without using expensive wide base-band converters. The digital filtering technique also enables a variety of observing modes defined on the VSOP terminal, even with a fixed sampling frequency in an A/D converter. The new terminals are installed at Nobeyama, Kashima, Usuda, Mizusawa, and Kagoshima radio observatories in Japan, and are being used in VSOP and other domestic VLBI observations. In this paper the key features of the VSOP terminal focusing on these advanced technologies are presented, and the results of performance tests are shown.

High-Tc superconductors convincingly showed that these materials are essentially natural arrays of Josephson junctions formed in atomic scale. In this paper, in-plane aligned a-axis-oriented YBa2Cu3O7-δ (YBCO) thin films were successfully grown on LaSrGaO4(LSGO) (100) substrates which were cleaned by ion-beam. Voltage jumps with hysteresis implying intrinsic Josephson effects are observed in c-axis direction. This result suggest that it is possible to achieve planar intrinsic Josephson devices which have applications in high frequency electronics, such as voltage standards, Josephson masers and so on.

A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.

A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

An efficient two-layer coding method using the histogram packing technique with the backward compatibility to the legacy JPEG is proposed in this paper. The JPEG XT, which is the international standard to compress HDR images, adopts two-layer coding scheme for backward compatibility to the legacy JPEG. However, this two-layer coding structure does not give better lossless performance than the other existing methods for HDR image compression with single-layer structure. Moreover, the lossless compression of the JPEG XT has a problem on determination of the coding parameters; The lossless performance is affected by the input images and/or the parameter values. That is, finding appropriate combination of the values is necessary to achieve good lossless performance. It is firstly pointed out that the histogram packing technique considering the histogram sparseness of HDR images is able to improve the performance of lossless compression. Then, a novel two-layer coding with the histogram packing technique and an additional lossless encoder is proposed. The experimental results demonstrate that not only the proposed method has a better lossless compression performance than that of the JPEG XT, but also there is no need to determine image-dependent parameter values for good compression performance without losing the backward compatibility to the well known legacy JPEG standard.

In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.

With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a promising solution to consider the process parameter variation but it has not been widely used yet. For estimating the delay yield, designers have to know and understand the accuracy of SSTA. However, the accuracy has not been thoroughly studied from a practical point of view. This paper proposes two metrics to measure the pessimism/optimism of SSTA; the first corresponds to yield estimation error, and the second examines delay estimation error. We apply the metrics for a problem which has been widely discussed in SSTA community, that is, normal-distribution approximation of max operation. We also apply the proposed metrics for benchmark circuits and discuss about a potential problem originating from normal-distribution approximation. Our metrics indicate that the appropriateness of the approximation depends on not only given input distributions but also the target yield of the product, which is an important message for SSTA users.

Clustering L0 buffers is effective for energy reduction in the instruction memory caches of embedded VLIW processors. However, the efficiency of the clustering depends on the schedule of the target application. For improving the energy efficiency of L0 clusters, an operation shuffling is proposed, which explores assignment of operations for each cycle, generates various schedules, and evaluates them to find an energy efficient schedule. This approach can find energy efficient schedules, however, it takes a long time to obtain the final result. In this paper, we propose a new method to directly generate an energy efficient schedule without iterations of operation shuffling. In the proposed method, a compiler schedules operations using the result of the single operation shuffling as a constraint. We propose some optimization algorithms to generate an energy efficient schedule for a given L0 cluster organization. The proposed method can drastically reduce the computational effort since it performs the operation shuffling only once. The experimental results show that comparable energy reduction is achieved by using the proposed method while the computational effort can be reduced significantly over the conventional operation shuffling.

B(P)SCCO films were prepared on MgO substrate by a double cathode dc sputtering with a mosaic BiχSrCaCuyOz and (Bi0.7Pb0.3)χ SrCaCuyOz target. The films were deposited at 200 and 550, and then annealed. We have obtained the B(P)SCCO films with Tc of 90-100 K under the condition of the deposition at 550 and the in-situ annealing in 200 Torr O2 and the post-deposition annealing at 860.

A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.

This paper discusses a method of designing linear phase two-channel filter banks for integer wavelet transform. We show that the designed filter banks are easily structed as the lifting form by leading relationship between designed filters and lifting structure. The designed integer wavelets are applied to image compression to verify the efficiency of our method.

We have developed a high-efficiency charge-pump power supply circuit with large output current capability for mobile equipment. However, during the commercialization phase, we found that the large inrush current of 270 mA at charge-pump circuit startup-time could cause problems. In this paper we analyze the mechanism that causes this inrush current, and we propose circuitry to reduce it. We show SPICE simulation and measurement results for our proposed circuitry that confirm its effectiveness. By incorporating this circuitry, startup-time inrush current was reduced to 30 mA.